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4:1 hdmi/dvi switch with equalization AD8191 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2006 analog devices, inc. all rights reserved. features four inputs, one output hdmi?/dvi links four tmds channels per link supports 250 mbps to 1.65 gbps data rates supports 25 mhz to 165 mhz pixel clocks equalized inputs for operatio n with long hdmi cables (20 meters at 1080p) fully buffered unidirectional inputs/outputs globally switchable, 50 on-chip terminations pre-emphasized outputs low added jitter single-supply operation (3.3 v) four auxiliary channels per link bidirectional unbuffered inputs/outputs flexible supply operation (3.3 v to 5 v) hdcp standard compatible allows switching of ddc bus and two additional signals multiple channel bundling modes 1x (4:1) hdmi/dvi link switch (default) 2x (8:1) tmds channel and auxiliary signal switch 1x (16:1) tmds channel and auxiliary signal switch output disable feature reduced power dissipation removable output termination allows building of larger arrays two AD8191s support hdmi/dvi dual-link standards compatible: hdmi receiver, dvi, hdcp serial (i 2 c? slave) and parallel control interface 100-lead, 14 mm 14 mm lqfp, pb-free package applications multiple input displays projectors a/v receivers set-top boxes advanced television (hdtv) sets functional block diagram low speed unbuffered high speed buffered avcc dvcc amuxvcc avee dvee vtto op[3:0] a ux_com[3:0] on[3:0] + ? 4 bidirectional i2c_sda i2c_scl i2c_addr[2:0] vtti vtti ip_a[3:0] in_a[3:0] + ? ip_b[3:0] in_b[3:0] + ? ip_c[3:0] in_c[3:0] + ? ip_d[3:0] in_d[3:0] aux_c[3:0] aux_b[3:0] aux_a[3:0] aux_d[3:0] + ? 4 4 4 4 4 4 4 4 4 4 4 4 eq switch core switch core control logic config interface 3 2 2 serial parallel pp_ch[1:0] pp_oto pp_ocl pp_eq pp_en pp_pre[1:0] reset pe 4 4 AD8191 0 6123-001 figure 1. typical application dvd player game console set-top box media center hdtv set hdmi receiver AD8191 01:18 06123-002 figure 2. typical hdtv application general description the AD8191 is a hdmi/dvi switch featuring equalized tmds inputs and pre-emphasized tmds outputs, ideal for systems with long cable runs. outputs can be set to a high impedance state to reduce the power dissipation and/or allow the construc- tion of larger arrays using the wire-or technique. flexible channel bundling modes (for both the tmds channels and the auxiliary signals) allow the AD8191 to be configured as a 4:1 single hdmi/dvi link switch, a dual 8:1 switch, or a single 16:1 switch. the AD8191 is provided in a 100-lead lqfp, pb-free, surface mount package specified to operate over the ?40c to +85c temperature range. product highlights 1. supports data rates up to 1.65 gbps, enabling 1080p hdmi formats and uxga (1600 1200) dvi resolutions. 2. input cable equalizer enables use of long cables at the input (more than 20 meters of 24 awg cable at 1080p). 3. auxiliary switch routes a ddc bus and two additional signals for a single-chip, hdmi 1.2a receive-compliant solution.
AD8191 rev. 0 | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 typical application ........................................................................... 1 general description ......................................................................... 1 product highlights ........................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 thermal resistance ...................................................................... 5 maximum power dissipation ..................................................... 5 esd caution .................................................................................. 5 pin configuration and function descriptions ............................. 6 typical performance characteristics ............................................. 9 theory of operation ...................................................................... 13 introduction ................................................................................ 13 input channels ............................................................................ 13 output channels ........................................................................ 13 high speed (tmds) switching modes ................................... 14 auxiliary switch .......................................................................... 14 auxiliary (low speed) switching modes ................................ 15 serial control interface .................................................................. 16 reset ............................................................................................. 16 wr ite pro cedure .......................................................................... 16 read procedure ........................................................................... 17 parallel control interface .............................................................. 18 serial interface configuration registers ..................................... 19 high speed device modes register ......................................... 19 auxiliary device modes register ............................................. 20 receiver settings register ......................................................... 22 input termination pulse register 1 and register 2 ............... 22 receive equalizer register 1 and register 2 ........................... 22 transmitter settings register .................................................... 22 parallel interface configuration registers .................................. 23 high speed device modes register ......................................... 23 auxiliary device modes register ............................................. 23 receiver settings register ......................................................... 24 input termination pulse register 1 and register 2 ............... 24 receive equalizer register 1 and register 2 ........................... 24 transmitter settings register .................................................... 24 application notes ........................................................................... 25 pinout ........................................................................................... 25 cable lengths and equalization ............................................... 25 pcb layout guidelines .............................................................. 26 outline dimensions ....................................................................... 30 ordering guide .......................................................................... 30 revision history 10/06revision 0: initial version
AD8191 rev. 0 | page 3 of 32 specifications t a = 27c, avcc = 3.3 v, vtti = 3.3 v, vtto = 3.3 v, dvcc = 3.3 v, amuxvcc = 5 v, avee = 0 v, dvee = 0 v, differential input swing = 1000 mv, tmds outputs terminated with external 50 resistors to 3.3 v, unless otherwise noted. table 1. parameter conditions/comments min typ max unit dynamic performance maximum data rate (dr) per channel nrz 1.65 gbps bit error rate (ber) prbs 2 23 ? 1 10 ?9 added deterministic jitter dr 1.65 gbps, prbs 2 23 ? 1 40 ps (p-p) added random jitter 2 ps (rms) differential intrapair sk ew at output 1 ps differential interpair skew 1 at output 40 ps equalization performance receiver (highest setting) 2 boost frequency = 825 mhz 12 db transmitter (highest setting) 3 boost frequency = 825 mhz 6 db input characteristics input voltage swing differential 150 1200 mv input common-mode voltage (v icm ) avcc ? 800 avcc mv output characteristics high voltage level single-ended high speed channel avcc ? 10 avcc + 10 mv low voltage level single-ended high speed channel avcc ? 600 avcc ? 400 mv rise/fall time (20% to 80%) 75 135 200 ps input termination resistance single-ended 50 auxiliary channels on resistance, r aux 100 on capacitance, c aux dc bias = 2.5 v, ac voltage = 3.5 v, f = 100 khz 8 pf input/output voltage range dvee amuxvcc v power supply avcc operating range 3 3.3 3.6 v quiescent current avcc outputs disabled 30 40 44 ma outputs enabled, no pre-emphasis 48 60 64 ma outputs enabled, maximum pre-emphasis 88 100 110 ma vtti input termination on 4 5 40 54 ma vtto output termination on, no pre-emphasis 35 40 46 ma output termination on, maximum pre-emphasis 72 80 90 ma dvcc 3.2 7 8 ma amuxvcc 0.01 0.1 ma power dissipation outputs disabled 115 271 361 mw outputs enabled, no pre-emphasis 384 574 671 mw outputs enabled, maximum pre-emphasis 704 910 1050 mw timing characteristics switching/update delay high speed switching register: hs_ch 200 ms all other configuration registers 1.5 ms reset pulse width 50 ns
AD8191 rev. 0 | page 4 of 32 parameter conditions/comments min typ max unit serial control interface 5 input high voltage, v ih 2 v input low voltage, v il 0.8 v output high voltage, v oh 2.4 v output low voltage, v ol 0.4 v parallel control interface input high voltage, v ih 2 v input low voltage, v il 0.8 v 1 differential interpair skew is measured between the tmds pairs of a single link. 2 AD8191 output meets the transmitte r eye diagram as defined in the dvi standard revision 1.0 and the hdmi standard revision 1.2 a. 3 cable output meets the receiver eye diagram mask as defined in the dvi standard revision 1.0 and the hdmi standard revision 1. 2a. 4 typical value assumes only the selected hdmi/dvi link is active with nominal signal swings and that the unselected hdmi/dvi li nks are deactivated. minimum and maximum limits are measured at the respec tive extremes of input termination resistance and input voltage swing. 5 the AD8191 is an i 2 c slave and its serial control interface is based on the 3.3 v i 2 c bus specification.
AD8191 rev. 0 | page 5 of 32 absolute maximum ratings table 2. parameter rating avcc to avee 3.7 v dvcc to dvee 3.7 v dvee to avee 0.3 v vtti avcc + 0.6 v vtto avcc + 0.6 v amuxvcc 5.5 v internal power dissipation 2.2 w high speed input voltage avcc ? 1.4 v < v in < avcc + 0.6 v high speed differential input voltage 2.0 v low speed input voltage dvee ? 0.3 v < v in < amuxvcc + 0.6 v i 2 c and parallel logic input voltage dvee ? 0.3 v < v in < dvcc + 0.6 v storage temperature range ?65c to +125c operating temperature range ?40c to +85c junction temperature 150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions: a device soldered in a 4-layer jedec circuit board for surface-mount packages. jc is specified for no airflow. table 3. thermal resistance package type ja jc unit 100-lead lqfp 56 19 c/w maximum power dissipation the maximum power that can be safely dissipated by the AD8191 is limited by the associated rise in junction temperature. the maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150c. te mporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of 175c for an extended period can result in device failure. to ensure proper operation, it is necessary to observe the maximum power rating as determined by the coefficients in table 3 . esd caution
AD8191 rev. 0 | page 6 of 32 pin configuration and fu nction descriptions pp_oto aux_a0 aux_a1 aux_a2 aux_a3 dvee aux_b0 aux_b1 aux_b2 aux_b3 aux_com0 aux_com1 aux_com2 aux_com3 aux_c0 aux_c1 aux_c2 aux_c3 amuxvcc aux_d0 aux_d1 aux_d2 aux_d3 pp_eq pp_en 26 i2c_addr0 27 i2c_addr1 28 i2c_addr2 29 dvee 30 pp_ch0 31 pp_ch1 32 dvcc 33 on0 34 op0 35 vtto 36 on1 37 op1 38 dvcc 39 on2 2 in_b0 3 ip_b0 4 avee 7 vtti 6 ip_b1 5 in_b1 1 avcc 8 in_b2 9 ip_b2 10 avee 12 ip_b3 13 avcc 14 in_a0 15 ip_a0 16 avee 17 in_a1 18 ip_a1 19 vtti 20 in_a2 21 ip_a2 22 avcc 23 in_a3 24 ip_a3 25 avee 11 in_b3 74 ip_c3 avcc 73 in_c3 72 avee 69 vtti 70 in_c2 71 ip_c2 75 68 ip_c1 67 in_c1 66 avee 64 in_c0 63 avcc 62 ip_d3 61 in_d3 60 avee 59 ip_d2 58 in_d2 57 vtti 56 ip_d1 55 in_d1 54 avcc 53 ip_d0 52 in_d0 51 avee 65 ip_c0 40 op2 41 vtto 42 on3 43 op3 44 reset 45 pp_pre0 46 pp_pre1 47 dvcc 48 pp_ocl 49 i2c_scl 50 i2c_sda 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 pin 1 indicator AD8191 top view (not to scale) 0 6123-003 figure 3. pin configuration table 4. pin function descriptions pin no. mnemonic type 1 description 1, 13, 22, 54, 63, 75 avcc power positive analog supply. 3.3 v nominal. 2 in_b0 hs i high speed input complement. 3 ip_b0 hs i high speed input. 4, 10, 16, 25, 51, 60, 66, 72 avee power negative analog supply. 0 v nominal. 5 in_b1 hs i high speed input complement. 6 ip_b1 hs i high speed input. 7, 19, 57, 69 vtti power input termination supply. nominally connected to avcc. 8 in_b2 hs i high speed input complement. 9 ip_b2 hs i high speed input. 11 in_b3 hs i high speed input complement. 12 ip_b3 hs i high speed input. 14 in_a0 hs i high speed input complement. 15 ip_a0 hs i high speed input.
AD8191 rev. 0 | page 7 of 32 pin no. mnemonic type 1 description 17 in_a1 hs i high speed input complement. 18 ip_a1 hs i high speed input. 20 in_a2 hs i high speed input complement. 21 ip_a2 hs i high speed input. 23 in_a3 hs i high speed input complement. 24 ip_a3 hs i high speed input. 26 i2c_addr0 control i 2 c address 1 st lsb. 27 i2c_addr1 control i 2 c address 2 nd lsb. 28 i2c_addr2 control i 2 c address 3 rd lsb. 29, 95 dvee power negative digital and auxiliary multiplexer power supply. 0 v nominal. 30 pp_ch0 control quad switching mode high speed source selection parallel interface lsb. 31 pp_ch1 control quad switching mode high speed source selection parallel interface msb. 32, 38, 47 dvcc power positive digital power supply. 3.3 v nominal. 33 on0 hs o high speed output complement. 34 op0 hs o high speed output. 35, 41 vtto power output termination supply. nominally connected to avcc. 36 on1 hs o high speed output complement. 37 op1 hs o high speed output. 39 on2 hs o high speed output complement. 40 op2 hs o high speed output. 42 on3 hs o high speed output complement. 43 op3 hs o high speed output. 44 reset control configuration registers reset. normally pulled up to avcc. 45 pp_pre0 control high speed pre-emphasis selection parallel interface lsb. 46 pp_pre1 control high speed pre-emphasis selection parallel interface msb. 48 pp_ocl control high speed output current level parallel interface. 49 i2c_scl control i 2 c clock. 50 i2c_sda control i 2 c data. 52 in_d0 hs i high speed input complement. 53 ip_d0 hs i high speed input. 55 in_d1 hs i high speed input complement. 56 ip_d1 hs i high speed input. 58 in_d2 hs i high speed input complement. 59 ip_d2 hs i high speed input. 61 in_d3 hs i high speed input complement. 62 ip_d3 hs i high speed input. 64 in_c0 hs i high speed input complement. 65 ip_c0 hs i high speed input. 67 in_c1 hs i high speed input complement. 68 ip_c1 hs i high speed input. 70 in_c2 hs i high speed input complement. 71 ip_c2 hs i high speed input. 73 in_c3 hs i high speed input complement. 74 ip_c3 hs i high speed input. 76 pp_en control high speed output enable parallel interface. 77 pp_eq control high speed equalization selection parallel interface. 78 aux_d3 ls i/o low speed input/output.
AD8191 rev. 0 | page 8 of 32 pin no. mnemonic type 1 description 79 aux_d2 ls i/o low speed input/output. 80 aux_d1 ls i/o low speed input/output. 81 aux_d0 ls i/o low speed input/output. 82 amuxvcc power positive auxiliary multiplexer supply. 5v typical. 83 aux_c3 ls i/o low speed input/output. 84 aux_c2 ls i/o low speed input/output. 85 aux_c1 ls i/o low speed input/output. 86 aux_c0 ls i/o low speed input/output. 87 aux_com3 ls i/o low speed common input/output. 88 aux_com2 ls i/o low speed common input/output. 89 aux_com1 ls i/o low speed common input/output. 90 aux_com0 ls i/o low speed common input/output. 91 aux_b3 ls i/o low speed input/output. 92 aux_b2 ls i/o low speed input/output. 93 aux_b1 ls i/o low speed input/output. 94 aux_b0 ls i/o low speed input/output. 96 aux_a3 ls i/o low speed input/output. 97 aux_a2 ls i/o low speed input/output. 98 aux_a1 ls i/o low speed input/output. 99 aux_a0 ls i/o low speed input/output. 100 pp_oto control high speed output termination selection parallel interface. 1 hs = high speed, ls = low speed, i = input, o = output.
AD8191 rev. 0 | page 9 of 32 typical performance characteristics t a = 27c, avcc = 3.3 v, vtti = 3.3 v, vtto = 3.3 v, dvcc = 3.3 v, amuxvcc = 5 v, avee = 0 v, dvee = 0 v, differential input swing = 1000 mv, tmds outputs terminated with external 50 resistors to 3.3 v, pattern = prbs 2 7 ? 1, data rate = 1.65 gbps, unless otherwise noted. reference eye diagram at tp1 digital pattern generator AD8191 evaluation board serial data analyzer sma coax cable hdmi cable tp1 tp2 tp3 0 6123-035 figure 4. test circuit diagram for rx eye diagram 0.125ui/div at 1.65gbps 250mv/di v 06123-036 figure 5. rx eye diagram at tp2 (cable = 2 meters, 30 awg) 0.125ui/div at 1.65gbps 250mv/di v 06123-037 figure 6. rx eye diagram at tp2 (cable = 20 meters, 24 awg) 0.125ui/div at 1.65gbps 250mv/di v 06123-038 figure 7. rx eye diagram at tp3, eq = 6 db (cable = 2 meters, 30 awg) 0.125ui/div at 1.65gbps 250mv/di v 06123-039 figure 8. rx eye diagram at tp3, eq = 12 db (cable = 20 meters, 24 awg)
AD8191 rev. 0 | page 10 of 32 t a = 27c, avcc = 3.3 v, vtti = 3.3 v, vtto = 3.3 v, dvcc = 3.3 v, amuxvcc = 5 v, avee = 0 v, dvee = 0 v, differential input swing = 1000 mv, tmds outputs terminated with external 50 resistors to 3.3 v, pattern = prbs 2 7 ? 1, data rate = 1.65 gbps, unless otherwise noted. reference eye diagram at tp1 digital pattern generator sma coax cable hdmi cable tp1 tp2 tp3 AD8191 evaluation board serial data analyzer 06123-040 figure 9. test circuit diagram for tx eye diagrams 0.125ui/div at 1.65gbps 250mv/di v 06123-041 figure 10. tx eye diagram at tp2, pe = 2 db 0.125ui/div at 1.65gbps 250mv/di v 06123-042 figure 11. tx eye diagram at tp2, pe = 6 db 0.125ui/div at 1.65gbps 250mv/di v 06123-043 figure 12. tx eye diagram at tp3, pe = 2 db (cable = 2 meters, 30 awg) 0.125ui/div at 1.65gbps 250mv/di v 06123-044 figure 13. tx diagram at tp3, pe = 6 db (cable = 10 meters, 28 awg)
AD8191 rev. 0 | page 11 of 32 t a = 27c, avcc = 3.3 v, vtti = 3.3 v, vtto = 3.3 v, dvcc = 3.3 v, amuxvcc = 5 v, avee = 0 v, dvee = 0 v, differential input swing = 1000 mv, tmds outputs terminated with external 50 resistors to 3.3 v, pattern = prbs 2 7 ? 1, data rate = 1.65 gbps, unless otherwise noted. 0.5 0.6 0 03 5 0.6 0 02 5 hdmi cable length (m) deterministic jitter (ui) hdmi cable length (m) deterministic jitter (ui) 0.4 0.3 0.2 0.1 5 1015202530 2m cable = 30awg 5m to 10m cables = 28awg 15m to 30m cables = 24awg 720p, eq = 12db 1080p, eq = 12db 480p, eq = 12db 1.65gbps, eq = 12db 06123-014 data rate (gbps) jitter (ps) figure 14. jitter vs. input cable length (see figure 4 for test setup) 60 0 01 . 8 50 40 30 20 10 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 dj (p-p) rj (rms) 06123-015 1.65gbps 1080p 1080i/720p 480p 480i figure 15. jitter vs. data rate 70 0 3.0 3.6 supply voltage (v) jitter (ps) 60 50 40 30 20 10 3.1 3.2 3.3 3.4 3.5 dj (p-p) rj (rms) 06123-016 figure 16. jitter vs. supply voltage 2m cable = 30awg 5m to 10m cables = 28awg 15m to 20m cables = 24awg 0.5 0.4 0.3 0.2 0.1 720p, pe off 5 101520 1080p, max pe 720p, max pe 480p, pe off 480p, max pe 1080p, pe off 06123-017 1200 0 01 . 8 data rate (gbps) eye height (mv) figure 17. jitter vs. output cable length (see figure 9 for test setup) 1000 800 600 400 200 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 06123-018 figure 18. eye height vs. data rate 800 0 3.0 3.6 supply voltage (v) eye height (mv) 700 600 500 400 300 200 100 3.1 3.2 3.3 3.4 3.5 06123-019 figure 19. eye height vs. supply voltage
AD8191 rev. 0 | page 12 of 32 differential input swing (mv) jitter (ps) t a = 27c, avcc = 3.3 v, vtti = 3.3 v, vtto = 3.3 v, dvcc = 3.3 v, amuxvcc = 5 v, avee = 0 v, dvee = 0 v, differential input swing = 1000 mv, tmds outputs terminated with external 50 resistors to 3.3 v, pattern = prbs 2 7 ? 1, data rate = 1.65 gbps, unless otherwise noted. 30 0 02 . 0 50 0 2.5 input common-mode voltage (v) jitter (ps) 25 20 15 10 5 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 dj (p-p) rj (rms) dj (p-p) rj (rms) 45 40 35 30 25 20 15 10 5 2.72.93.13.33.53.7 06123-023 06123-020 figure 20. jitter vs. differential input swing 0 ?60 100 temperature (c) jitter (ps) ?40 ?20 0 20 40 60 80 40 50 30 20 10 rj (rms) dj (p-p) 06123-021 figure 21. jitter vs. temperature 160 0 ?40 100 temperature (c) rise/fall time 20% to 80% (ps) 140 120 100 80 60 40 20 ?20 0 20 40 60 80 rise time fall time 06123-022 figure 22. rise and fall time vs. temperature figure 23. jitter vs. input common-mode voltage 120 80 ?40 100 temperature (c) differential input termination resistance ( ? ) 115 110 105 100 95 90 85 ?200 20406080 06123-024 figure 24. differential input termination resistance vs. temperature
AD8191 rev. 0 | page 13 of 32 theory of operation introduction the primary function of the AD8191 is to switch one of four (hdmi or dvi) single-link sources to one output. each hdmi/dvi link consists of four differential, high speed channels and four auxiliary single-ended, low speed control signals. the high speed channels include a data-word clock and three transition minimized differential signaling (tmds) data channels running at 10 the data-word clock frequency for data rates up to 1.65 gbps. the four low speed control signals are 5 v tolerant bidirectional lines that can carry configuration signals, hdcp encryption, and other information, depending upon the specific application. all four high speed tmds channels in a given link are identical; that is, the pixel clock can be run on any of the four tmds channels. transmit and receive channel compensation is provided for the high speed channels where the user can (manually) select among a number of fixed settings. the AD8191 switching logic has three modes: quad mode (a quad 4:1 switch), dual mode (a dual 8:1 switch) and single mode (one 16:1 switch). the AD8191 has two control interfaces. users have the option of controlling the part through either the parallel control interface or the i 2 c serial control interface. the AD8191 has eight user-programmable i 2 c slave addresses to allow multiple AD8191s to be controlled by a single i 2 c bus. a reset pin is provided to restore the control registers of the AD8191 to default values. in all cases, serial programming values override any prior parallel programming values and any use of the serial control interface disables the parallel control interface until the AD8191 is reset. when using the serial control interface, all three switching modes (quad, dual, and single) are accessible and the high speed channel switching mode is controlled independently of the auxiliary signal switching mode. when using the parallel control interface, only the quad switching mode is accessible, and the same channel select bus (pp_ch[1:0]) simultaneously switches both the high speed channels and the auxiliary signals. input channels each high speed input differential pair terminates to the 3.3 v vtti power supply through a pair of single-ended 50 on- chip resistors, as shown in figure 25 . the input terminations can be optionally disconnected for approximately 100 ms following a source switch. the user can program which of the 16 high speed input channels employs this feature by selectively programming the associated rx_pt bits in the input termination pulse register through the serial control interface. additionally, all the input terminations can be disconnected by programming the rx_to bit in the receiver settings register. by default, the input termination is enabled. the input terminations are enabled and cannot be switched when programming the AD8191 through the parallel control interface. cable eq 50? 50? ip_xx in_xx avee v tti 0 6123-004 figure 25. high speed input simplified schematic the input equalizer can be manually configured to provide two different levels of high frequency boost: 6 db or 12 db. the user can individually control the equalization level of the eight high speed input channels by selectively programming the associated rx_eq bits in the receive equalizer register through the serial control interface. alternately, the user can globally control the equalization level of all eight high speed input channels by setting the pp_eq pin of the parallel control interface. no specific cable length is suggested for a particular equalization setting because cable performance varies widely between manufacturers; however, in general, the equalization of the AD8191 can be set to 12 db without degrading the signal integrity, even for short input cables. at the 12 db setting, the AD8191 can equalize more than 20 meters of 24 awg cable at 1.65 gbps. output channels each high speed output differential pair is terminated to the 3.3 v vtto power supply through a 50 on-chip resistor ( figure 26 ). this termination is user-selectable; it can be turned on or off by programming the tx_pto bit of the transmitter settings register through the serial control interface, or by setting the pp_oto pin of the parallel control interface. the output termination resistors of the AD8191 back-terminate the output tmds transmission lines. these back-terminations act to absorb reflections from impedance discontinuities on the output traces, improving the signal integrity of the output traces and adding flexibility to how the output traces can be routed. for example, interlayer vias can be used to route the AD8191 tmds outputs on multiple layers of the pcb without severely degrading the quality of the output signal. the AD8191 output has a disable feature that places the outputs in a tristate mode. this mode is enabled by programming the hs_en bit of the high speed device modes register through the serial control interface or by setting the pp_en pin of the parallel control interface. larger wire-ored arrays can be constructed using the AD8191 in this mode.
AD8191 rev. 0 | page 14 of 32 v tto 50? 50 ? opx onx avee disable i out 0 6123-005 figure 26. high speed output simplified schematic the AD8191 requires output termination resistors when the high speed outputs are enabled. termination can be internal and/or external. the internal terminations of the AD8191 are enabled by programming the tx_pto bit of the transmitter settings register or by setting the pp_oto pin of the parallel control interface. the internal terminations of the AD8191 default to the setting indicated by pp_oto upon reset. external terminations can be provided either by on-board resistors or by the input termination resistors of an hdmi/dvi receiver. if both the internal terminations are enabled and external termi- nations are present, set the output current level to 20 ma by programming the tx_ocl bit of the transmitter settings register through the serial control interface or by setting the pp_ocl pin of the parallel control interface. the output current level defaults to the level indicated by pp_ocl upon reset. if only external terminations are provided (if the internal terminations are disabled), set the output current level to 10 ma by programming the tx_ocl bit of the transmitter settings register or by setting the pp_ocl pin of the parallel control interface. the high speed outputs must be disabled if there are no output termination resistors present in the system. the output pre-emphasis can be manually configured to provide one of four different levels of high frequency boost. the specific boost level is selected by programming the tx_pe bits of the transmitter settings register through the serial control interface, or by setting the pp_pe bus of the parallel control interface. no specific cable length is suggested for a particular pre-emphasis setting because cable performance varies widely between manufacturers. high speed (tmds) switching modes the AD8191 has three high speed switching modes: quad, dual, and single. these are selected by programming the hs_sm bits of the high speed device modes register through the serial control interface. quad switching mode this is the default mode. in quad mode, the AD8191 behaves like a 4:1 hdmi/dvi link multiplexer routing groups of four tmds input channels to the four-channel output. this mode is accessible through both the serial and the parallel control interfaces. when using the serial control interface, the user selects which tmds link is routed to the output by programming the hs_ch bits of the high speed device modes register in accordance with the switch mapping listed in table 8 . when using the parallel control interface, the user selects which tmds link is routed to the output by setting the pp_ch bus of the parallel control interface in accordance with the switch mapping listed in table 26 . dual switching mode in this mode, the AD8191 behaves as a locked dual [8:1] tmds channel switch. the two 8:1 switches share the channel select input and, therefore, switch together. the user selects which two out of the eight possible input groups are routed to output by programming the hs_ch bits of the high speed device modes register in accordance with the switch mapping listed in table 9 . this mode is only accessible through the serial control interface. single switching mode in this mode, the AD8191 behaves as a single 16:1 tmds channel multiplexer; one of the 16 input channels is routed to all of the outputs. the user selects which input channel is routed to the outputs by programming the hs_ch bits in the high speed device modes register in accordance with the switch mapping listed in table 10 . this mode is only accessible through the serial control interface. auxiliary switch the auxiliary (low speed) lines have no amplification. they are routed using a passive switch that is bandwidth compatible with standard speed i 2 c. the schematic equivalent for this passive connection is shown in figure 27 . aux_com0 aux_a0 ?c aux ?c aux r aux 06123-006 figure 27. auxiliary channel simplified schematic, aux_a0 to aux_com0 routing example when turning off the AD8191, care needs to be taken with the amuxvcc supply to ensure that the auxiliary multiplexer pins remain in a high impedance state. a scenario that illustrates this requirement is one where the auxiliary multiplexer is used to switch the display data channel (ddc) bus. in some applica- tions, additional devices can be connected to the ddc bus (such as an eeprom with edid information) upstream of the AD8191. extended display identification data (edid) is a vesa standard-defined data format for conveying display configuration information to sources to optimize display use. edid devices may need to be available via the ddc bus, regardless of the state of the AD8191 and any downstream circuit. for this configuration, the auxiliary inputs of the powered down AD8191 need to be in a high impedance state to avoid pulling down on the ddc lines and preventing these other devices from using the bus. when the AD8191 is powered from a simple resistor network, as shown in figure 28 , it uses the 5 v supply that is required from any hdmi/dvi source to guarantee high impedance of
AD8191 rev. 0 | page 15 of 32 the auxiliary multiplexer pins. the amuxvcc supply does not draw any static current; therefore, it is recommended that the resistor network tap the 5 v supplies as close to the connectors as possible to avoid any additional voltage drop. this precaution does not need to be taken if the ddc peripheral circuitry is connected to the bus downstream of the AD8191. peripheral circuitry peripheral circuitry +5v source c +5v source d pin 18 hdmi connector pin 14 dvi connector pin 18 hdmi connector pin 14 dvi connector 10k ? 10m ? 10k ? |<50ma |<50ma peripheral circuitry peripheral circuitry source a +5v source b +5v pin 18 hdmi connector pin 14 dvi connector pin 18 hdmi connector pin 14 dvi connector 10k ? 10k ? |<50ma |<50ma amuxvcc AD8191 +5v internal (if any) 0 6123-007 figure 28. suggested amuxvcc power scheme auxiliary (low speed) switching modes the AD8191 has three auxiliary switching modes: quad, dual, and single. these are selected by programming the aux_sm bits of the auxiliary device modes register through the serial control interface. the auxiliary switching mode is independent of the high speed switching mode whenever the part is controlled through the serial control interface. when the part is controlled through the parallel control interface, however, only quad mode is accessible and the auxiliary switching mode cannot be independently controlled. quad switching mode this is the default mode. in quad mode, the AD8191 behaves like a 4:1 auxiliary link multiplexer, routing groups of four auxiliary input signals to the four-signal output. the user can select which group of inputs is routed to the output by program- ming the aux_ch bits of the auxiliary device modes register through the serial control interface in accordance with the switch mapping listed in table 13 . alternately, the user can select which group of inputs is routed to the output by setting the pp_ch bus of the parallel control interface in accordance with the switch mapping listed in table 27 . dual switching mode in this mode, the AD8191 behaves as a locked dual [8:1] auxiliary signal switch. the two 8:1 switches share the channel select input and, therefore, switch together. the user selects which two out of the eight possible input groups are routed to the output by programming the aux_ch bits of the auxiliary device modes register in accordance with the switch mapping listed in table 14 . this mode is only accessible through the serial control interface. single switching mode in this mode the AD8191 behaves as a single 16:1 tmds channel multiplexer; a single channel, out of a possible 16, is routed to all of the outputs. the user selects which input channel is routed to the outputs by programming the aux_ch bits of the auxiliary device modes register in accordance with the switch mapping listed in table 15 . this mode is only accessible through the serial control interface.
AD8191 rev. 0 | page 16 of 32 serial control interface reset on initial power-up, or at any point in operation, the AD8191 register set can be restored to preprogrammed default values by pulling the reset pin to low in accordance with the specifica- tions in table 1 . during normal operation, however, the reset pin must be pulled up to 3.3 v. following a reset, the prepro- grammed default values of the AD8191 register set correspond to the state of the parallel interface configuration registers, as listed in table 24 . the AD8191 can be controlled through the parallel control interface until the first serial control event occurs. as soon as any serial control event occurs, the serial programming values, corresponding to the state of the serial interface configuration registers ( table 5 ), override any prior parallel programming values, and the parallel control interface is disabled until the part is subsequently reset. write procedure to write data to the AD8191 register set, an i 2 c master (such as a microcontroller) needs to send the appropriate control signals to the AD8191 slave device. the signals are controlled by the i 2 c master, unless otherwise specified. for a diagram of the procedure, see figure 29 . the steps for a write procedure are as follows: 1. send a start condition (while holding the i2c_scl line high, pull the i2c_sda line low). 2. send the AD8191 part address (seven bits). the upper four bits of the AD8191 part address are the static value [1001] and the three lsbs are set by input pin i2c_addr2, input pin i2c_addr1, and input pin i2c_addr0 (lsb). this transfer should be msb first. 3. send the write indicator bit (0). 4. wait for the AD8191 to acknowledge the request. 5. send the register address (eight bits) to which data is to be written. this transfer should be msb first. 6. wait for the AD8191 to acknowledge the request. 7. send the data (eight bits) to be written to the register whose address was set in step 5. this transfer should be msb first. 8. wait for the AD8191 to acknowledge the request. 9. perform one of the following: 9a. send a stop condition (while holding the i2c_scl line high, pull the i2c_sda line high) and release control of the bus to end the transaction (shown in figure 29 ). 9b. send a repeated start condition (while holding the i2c_scl line high, pull the i2c_sda line low) and continue with step 2 in this procedure to perform another write. 9c. send a repeated start condition (while holding the i2c_scl line high, pull the i2c_sda line low) and continue with step 2 of the read procedure (in the read procedure section) to perform a read from another address. 9d. send a repeated start condition (while holding the i2c_scl line high, pull the i2c_sda line low) and continue with step 8 of the read procedure (in the read procedure section) to perform a read from the same address set in step 5. r/w ack ack addr start fixed part addr register addr data stop ack 1 2 3 4 5 6 7 8 9 i2c_scl general case i2c_sda example i2c_sda *the switching/update delay begins at the falling edge of the last data bit; for example, the falling edge just before step 8. * 06123-008 figure 29. i 2 c write diagram
AD8191 rev. 0 | page 17 of 32 start fixed part addr register addr fixed part addr data stop ack addr ack r/w addr ack ack r/w sr 1 2 3 4 5 6 7 8 9 10 11 12 13 i2c_scl general case i2c_sda example i2c_sda 06123-009 figure 30. i 2 c read diagram read procedure to read data from the AD8191 register set, an i 2 c master (such as a microcontroller) needs to send the appropriate control signals to the AD8191 slave device. the signals are controlled by the i 2 c master, unless otherwise specified. for a diagram of the procedure, see figure 30 . the steps for a read procedure are as follows: 1. send a start condition (while holding the i2c_scl line high, pull the i2c_sda line low). 2. send the AD8191 part address (seven bits). the upper four bits of the AD8191 part address are the static value [1001] and the three lsbs are set by input pin i2c_addr2, input pin i2c_addr1, and input pin i2c_addr0 (lsb). this transfer should be msb first. 3. send the write indicator bit (0). 4. wait for the AD8191 to acknowledge the request. 5. send the register address (eight bits) from which data is to be read. this transfer should be msb first. 6. wait for the AD8191 to acknowledge the request. 7. send a repeated start condition (sr) by holding the i2c_scl line high and pulling the i2c_sda line low. 8. resend the AD8191 part address (seven bits) from step 2. the upper four bits of the AD8191 part address are the static value [1001] and the three lsbs are set by the input pin i2c_addr2, i2c_addr1 and input pin i2c_addr0 (lsb). this transfer should be msb first. 9. send the read indicator bit (1). 10. wait for the AD8191 to acknowledge the request. 11. the AD8191 serially transfers the data (eight bits) held in the register indicated by the address set in step 5. this data is sent msb first. 12. acknowledge the data from the AD8191. 13. perform one of the following: 13a. s op condition (while holding the i2c_scl line high, pull the sda line high) and release control of the bus to end the transaction (shown in end a st ). 13b. ated start condition (while holding the 13c. 13d. on (while holding the figure 30 send a repe i2c_scl line high, pull the i2c_sda line low) and continue with step 2 of the write procedure (previous wr ite pro cedure section) to perform a write. send a repeated start condition (while holding the i2c_scl line high, pull the i2c_sda line low) and continue with step 2 of this procedure to perform a read from another address. send a repeated start conditi i2c_scl line high, pull the i2c_sda line low) and continue with step 8 of this procedure to perform a read from the same address.
AD8191 rev. 0 | page 18 of 32 parallel control interface the AD8191 can be controlled through the parallel interface using the pp_en, pp_ch[1:0], pp_eq, pp_pre[1:0], pp_oto, and pp_ocl pins. logic levels for the parallel interface pins are set in accordance with the specifications listed in table 1 . setting these pins updates the parallel control interface registers, as listed in table 24 . following a reset, the AD8191 can be controlled through the parallel control interface until the first serial control event occurs. as soon as any serial control event occurs, the serial programming values override any prior parallel programming values, and the parallel control interface is disabled until the part is subsequently reset. the default serial programming values correspond to the state of the serial interface configuration registers, as listed in table 5 .
AD8191 rev. 0 | page 19 of 32 serial interface configuration registers the serial interface configuration registers can be read and written using the i 2 c serial control interface, pin i2c_sda, and pin i2c_scl. the least significant bits of the AD8191 i 2 c part address are set by tying the pin i2c_addr2, pin i2c_addr1, and pin i2c_addr0 to 3.3 v (logic 1) or 0 v (logic 0). as soon as the serial control interface is used, the parallel control interface is disabled u ntil the AD8191 is reset as described in the serial control interface section. table 5. serial (i 2 c) interface register map name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 addr. default high speed switch enable high speed switching mode select high speed source select high speed device modes hs_en hs_sm[1] hs_sm[0] hs_ch[3] hs_ch[2] hs_ch[1] hs_ch[0] 0x00 0x40 auxiliary switch enable auxiliary switching mode select auxiliary switch source select auxiliary device modes aux_en aux_sm[1] aux_sm[0] aux_ch [3] aux_ch[2] aux_ch[1] aux_ch[0] 0x01 0x40 high speed input termination select receiver settings rx_to 0x10 0x01 source a and source b : input termination pulse-on-source switch select (disconnect termination for a short period of time) input termination pulse 1 rx_pt[7] rx_pt[6] rx_pt[5] rx_pt[4] rx_pt[3] rx_pt[2] rx_pt[1] rx_pt [0] 0x11 0x00 source c and source d: input termination pulse-on-source switch select (disconnect termination for a short period of time) input termination pulse 2 rx_pt[15] rx_pt[14] rx_pt[13] rx_pt[12] rx_pt[11] rx_pt[10] rx_pt[9] rx_pt[8] 0x12 0x00 source a and source b: input equalization level select receive equalizer 1 rx_eq[7] rx_eq[6] rx_eq[5] rx_eq[4] rx_eq[3] rx_eq[2] rx_eq[1] rx_eq[0] 0x13 0x00 source c and source d: input equalization level select receive equalizer 2 rx_eq[15] rx_eq[14] rx_eq[13] rx_eq[12] rx_eq[11] rx_eq[10] rx_eq[9] rx_eq[8] 0x14 0x00 high speed output pre-emphasis level select high speed output termination select high speed output current level select transmitter settings tx_pe[1] tx_pe[0] tx_pto tx_ocl 0x20 0x03 high speed device modes register hs_en: high speed (tmds) channels enable bit table 6. hs_en description hs_en description 0 high speed channels off, low power/standby mode 1 high speed channels on hs_sm[1:0]: high speed (tmds) switching mode select bus table 7. hs_sm description hs_sm[1:0] description 00 quad mode, 4 [4:1] 01 dual mode, 2 [8:1] 10 single mode, 1 [16:1] 11 illegal value; previous value of hs_sm[1:0] retained hs_ch[3:0]: high speed (tmds) switch source select bus table 8. quad mode, 4 [4:1], high speed switch mapping hs_ch[3:0] o[3:0] description xx00 a[3:0] high speed source a switched to output xx01 b[3:0] high speed source b switched to output xx10 c[3:0] high speed source c switched to output xx11 d[3:0] high speed source d switched to output
AD8191 rev. 0 | page 20 of 32 table 9. dual mode, 2 [8:1], high speed switch mapping hs_ch[3:0] o[3:2] o[1:0] description x000 a1 a0 the a0 and a1 high speed channels switched to output x001 a3 a2 the a2 and a3 high speed channels switched to output x010 b1 b0 the b0 and b1 high speed channels switched to output x011 b3 b2 the b2 and b3 high speed channels switched to output x100 c1 c0 the c0 and c1 high speed channels switched to output x101 c3 c2 the c2 and c3 high speed channels switched to output x110 d1 d0 the d0 and d1 high speed channels switched to output x111 d3 d2 the d2 and d3 high speed channels switched to output table 10. single mode, 1 [16:1], high speed switch mapping hs_ch[3:0] o[3:0] description 0000 a0 high speed channel a0 switched to output 0001 a1 high speed channel a1 switched to output 0010 a2 high speed channel a2 switched to output 0011 a3 high speed channel a3 switched to output 0100 b0 high speed channel b0 switched to output 0101 b1 high speed channel b1 switched to output 0110 b2 high speed channel b2 switched to output 0111 b3 high speed channel b3 switched to output 1000 c0 high speed channel c0 switched to output 1001 c1 high speed channel c1 switched to output 1010 c2 high speed channel c2 switched to output 1011 c3 high speed channel c3 switched to output 1100 d0 high speed channel d0 switched to output 1101 d1 high speed channel d1 switched to output 1110 d2 high speed channel d2 switched to output 1111 d3 high speed channel d3 switched to output auxiliary device modes register aux_en: auxiliary (low speed) switch enable bit table 11. aux_en description aux_en description 0 auxiliary switch off, no low speed input/output to low speed common input/output connection 1 auxiliary switch on aux_sm[1:0]: auxiliary (low speed) switching mode select bus table 12. aux_sm[1:0] description aux_sm[1:0] description 00 quad mode, 4 [4:1] 01 dual mode, 2 [8:1] 10 single mode, 1 [6:1] 11 illegal value; previous value of aux_sm[1:0] retained aux_ch[3:0]: auxiliary (low speed) switch source select bus table 13. quad mode, 4 [4:1], auxiliary switch mapping aux_ch[3:0] aux_com[3:0] description xx00 aux_a[3:0] auxiliary source a switched to output xx01 aux_b[3:0] auxiliary source b switched to output xx10 aux_c[3:0] auxiliary source c switched to output xx11 aux_d[3:0] auxiliary source d switched to output
AD8191 rev. 0 | page 21 of 32 table 14. dual mode, 2 [8:1 ], auxiliary switch mapping aux_ch[3:0] aux_com[3:2] aux_com[1:0] description x000 aux_c0 aux_a0 the a0 and c0 auxiliary channels switched to output x001 aux_c1 aux_a1 the a1 and c1 auxiliary channels switched to output x010 aux_c2 aux_a2 the a2 and c2 auxiliary channels switched to output x011 aux_c3 aux_a3 the a3 and c3 auxiliary channels switched to output x100 aux_d0 aux_b0 the b0 and d0 auxiliary channels switched to output x101 aux_d1 aux_b1 the b1 and d1 auxiliary channels switched to output x110 aux_d2 aux_b2 the b2 and d2 auxiliary channels switched to output x111 aux_d3 aux_b3 the b3 and d3 auxiliary channels switched to output table 15. single mode, 1 [16:1], auxiliary switch mapping aux_ch[3:0] aux_com[3:0] description 0000 aux_a0 auxiliary channel a0 switched to output 0001 aux_a1 auxiliary channel a1 switched to output 0010 aux_a2 auxiliary channel a2 switched to output 0011 aux_a3 auxiliary channel a3 switched to output 0100 aux_b0 auxiliary channel b0 switched to output 0101 aux_b1 auxiliary channel b1 switched to output 0110 aux_b2 auxiliary channel b2 switched to output 0111 aux_b3 auxiliary channel b3 switched to output 1000 aux_c0 auxiliary channel c0 switched to output 1001 aux_c1 auxiliary channel c1 switched to output 1010 aux_c2 auxiliary channel c2 switched to output 1011 aux_c3 auxiliary channel c3 switched to output 1100 aux_d0 auxiliary channel d0 switched to output 1101 aux_d1 auxiliary channel d1 switched to output 1110 aux_d2 auxiliary channel d2 switched to output 1111 aux_d3 auxiliary channel d3 switched to output
AD8191 rev. 0 | page 22 of 32 receiver settings register rx_to: high speed (tmds) channels input termination on/off select bit table 16. rx_to description rx_to description 0 input termination off 1 input termination on (can be pulsed on and off according to settings in the input termination pulse register) input termination pulse register 1 and register 2 rx_pt[x]: high speed (tmds) input channel x pulse-on-source switch select bit table 17. rx_pt[x] description rx_pt[x] description 0 input termination for tmds channel x always connected when source is switched 1 input termination for tmds channel x disconnected for 100 ms when source switched table 18. rx_pt[x] mapping rx_pt[x] corresponding input tmds channel bit 0 b0 bit 1 b1 bit 2 b2 bit 3 b3 bit 4 a0 bit 5 a1 bit 6 a2 bit 7 a3 bit 8 c3 bit 9 c2 bit 10 c1 bit 11 c0 bit 12 d3 bit 13 d2 bit 14 d1 bit 15 d0 receive equalizer register 1 and register 2 rx_eq[x]: high speed (tmds) input x equalization level select bit table 19. rx_eq[x] description rx_eq[x] description 0 low equalization (6 db) 1 high equalization (12 db) table 20. rx_eq[x] mapping rx_eq[x] corresponding input tmds channel bit 0 b0 bit 1 b1 bit 2 b2 bit 3 b3 bit 4 a0 bit 5 a1 bit 6 a2 bit 7 a3 bit 8 c3 bit 9 c2 bit 10 c1 bit 11 c0 bit 12 d3 bit 13 d2 bit 14 d1 bit 15 d0 transmitter settings register tx_pe[1:0]: high speed (tmds) output pre-emphasis level select bus (for all tmds channels) table 21. tx_pe[1:0] description tx_pe[1:0] description 00 no pre-emphasis (0 db) 01 low pre-emphasis (2 db) 10 medium pre-emphasis (4 db) 11 high pre-emphasis (6 db) tx_pto: high speed (tmds) output termination on/off select bit (for all channels) table 22. tx_pto description tx_pto description 0 output termination off 1 output termination on tx_ocl: high speed (tmds) output current level select bit (for all channels) table 23. tx_ocl description tx_ocl description 0 output current set to 10 ma 1 output current set to 20 ma
AD8191 rev. 0 | page 23 of 32 parallel interface configuration registers the parallel interface configuration registers can be directly set using the pp_en, pp_ch[1:0], pp_eq, pp_pre[1:0], pp_oto, and pp_ocl pins. this interface is only accessible after the part is reset and before any registers are accessed using the serial c ontrol interface. the state of each pin is set by tying it to 3.3 v (logic 1) or 0 v (logic 0). table 24. parallel interface register map name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 high speed switch enable high speed switching mode select (quad) high speed source select high speed device modes pp_en 0 0 0 0 pp_ch[1] pp_ch[0] auxiliary switch enable auxiliary switching mode select (quad) auxiliary switch source select auxiliary device modes 1 0 0 0 0 pp_ch[1] pp_ch[0] input term. on/off select (termination always on) receiver settings 1 source a and source b input termination pulse-on- source switch select (termination always on) input termination pulse 1 0 0 0 0 0 0 0 0 source c and source d input termination pulse-on- source switch select (termination always on) input termination pulse 2 0 0 0 0 0 0 0 0 source a and source b input equalization level select receive equalizer 1 pp_eq pp_eq pp_eq pp_eq pp_eq pp_eq pp_eq pp_eq source c and source d input equalization level select receive equalizer 2 pp_eq pp_eq pp_eq pp_eq pp_eq pp_eq pp_eq pp_eq output pre-emphasis level select output termination on/off select output current level select transmitter settings pp_pe[1] pp_pe[0] pp_oto pp_ocl high speed device modes register the high speed (tmds) switching mode is fixed to quad mode when using the parallel interface. pp_en: high speed (tmds) channels enable bit table 25. pp_en description pp_en description 0 high speed channels off, low power/standby mode 1 high speed channels on pp_ch[1:0]: high speed (tmds) switch source select bus table 26. quad high speed switch mode mapping pp_ch[1:0] o[3:0] description 00 a[3:0] high speed source a switched to output 01 b[3:0] high speed source b switched to output 10 c[3:0] high speed source c switched to output 11 d[3:0] high speed source d switched to output auxiliary device modes register the auxiliary (low speed) switch is always enabled and the auxiliary switching mode is fixed to quad mode when using the parallel interface. pp_ch[1:0]: auxiliary switch source select bus table 27. quad auxiliary switch mode mapping pp_ch[1:0] aux_com[3:0] description 00 aux_a[3:0] auxiliary source a switched to output 01 aux_b[3:0]0 auxiliary source b switched to output 10 aux_c[3:0] auxiliary source c switched to output 11 aux_d[3:0] auxiliary source d switched to output
AD8191 rev. 0 | page 24 of 32 receiver settings register high speed (tmds) channels input termination is fixed to on when using the parallel interface. input termination pulse register 1 and register 2 high speed input (tmds) channels pulse-on-source switching fixed to off when using the parallel interface. receive equalizer register 1 and register 2 pp_eq: high speed (tmds) inputs equalization level select bit (for all tmds input channels) the input equalization cannot be set individually (per channel) when using the parallel interface; one equalization setting affects all input channels. table 28. pp_eq description pp_eq description 0 low equalization (6 db) 1 high equalization (12 db) transmitter settings register pp_pe[1:0]: high speed (tmds) output pre-emphasis level select bus (for all tmds channels) table 29. pp_pe[1:0] description pp_pe[1:0] description 00 no pre-emphasis (0 db) 01 low pre-emphasis (2 db) 10 medium pre-emphasis (4 db) 11 high pre-emphasis (6 db) pp_oto: high speed (tmds) output termination on/off select bit (for all tmds channels) table 30. pp_oto description pp_oto description 0 output termination off 1 output termination on pp_ocl: high speed (tmds) outp ut current level select bit (for all tmds channels) table 31. tx_ocl description pp_ocl description 0 output current set to 10 ma 1 output current set to 20 ma
AD8191 rev. 0 | page 25 of 32 application information 0 6123-031 figure 31. layout of the tmds traces on the AD8191 evaluation board (only top signal routing layer is shown) the AD8191 is an hdmi/dvi switch featuring equalized tmds inputs and pre-emphasized tmds outputs. it is in- tended for use as a 4:1 switch in systems with long cable runs on both the input and/or the output, and is fully hdmi 1.2a receive-compliant. pinout the AD8191 is designed for an hdmi/dvi receiver pinout at its input and a transmitter pinout at its output. this makes the AD8191 ideal for use in avr-type applications where the designer routes both the inputs and the outputs directly to hdmi/dvi connectors. this type of layout is used on the AD8191 evaluation board, as shown in figure 31 . when the AD8191 is used in receiver type applications, it is necessary to change the ordering of the output pins on the pcb to match up with the on-board receiver. one advantage of the AD8191 in an avr-type application is that all of the high speed signals can be routed on one side (the topside) of the board, as shown in figure 31 . in addition to 12 db of input equalization, the AD8191 provides up to 6 db of output pre-emphasis that boosts the output tmds signals and allows the AD8191 to precompensate when driving long pcb traces or output cables. the net effect of the input equalization and output pre-emphasis of the AD8191 is that the AD8191 can compensate for the signal degradation of both input and output cables; it acts to reopen a closed input data eye and transmit a full-swing hdmi signal to an end receiver. the AD8191 also provides a distinct advantage in receive-type applications because it is a fully buffered hdmi/dvi switch. although inverting the output pin order of the AD8191 on the pcb requires a designer to place vias in the high speed signal path, the AD8191 fully buffers and electrically decouples the outputs from the inputs. consequently, the effects of the vias placed on the output signal lines are not seen at the input of the AD8191. the programmable output terminations also improve signal quality at the output of the AD8191. therefore, the pcb designer has significantly improved flexibility in the placement and routing of the output signal path with the AD8191 over other solutions. cable lengths and equalization the AD8191 offers two levels of programmable equalization for the high speed inputs: 6 db and 12 db. the equalizer of the AD8191 is optimized for video data rates of 1.65 gbps. it can equalize up to 20 meters of 24 awg hdmi cable at data rates corresponding to the video format, 1080p.
AD8191 rev. 0 | page 26 of 32 the length of cable that can be used in a typical hdmi/dvi application depends on a large number of factors, including: ? cable quality: the quality of the cable in terms of conductor wire gauge and shielding. thicker conductors have lower signal degradation per unit length. ? data rate: the data rate being sent over the cable. the signal degradation of hdmi cables increases with data rate. ? edge rates: the edge rates of the source input. slower input edges result in more significant data eye closure at the end of a cable. ? receiver sensitivity: the sensitivity of the terminating receiver. as such, specific cable types and lengths are not recommended for use with a particular equalizer setting. in nearly all applica- tions, the AD8191 equalization level can be set to high, or 12 db, for all input cable configurations at all data rates, without degrading the signal integrity. pcb layout guidelines the AD8191 is used to switch two distinctly different types of signals, both of which are required for hdmi and dvi video. these signal groups require different treatment when laying out a pc board. the first group of signals carries the audiovisual (av) data. hdmi/dvi video signals are differential, unidirectional, and high speed (up to 1.65 gbps). the channels that carry the video data must be controlled impedance, terminated at the receiver, and capable of operating up to at least 1.65 gbps. it is especially important to note that the differential traces that carry the tmds signals should be designed with a controlled differential impedance of 100 . the AD8191 provides single-ended, 50 terminations on-chip for both its inputs and outputs, and both the input and output terminations can be enabled or disabled through the serial interface. transmitter termination is not fully specified by the hdmi standard but its inclusion improves the overall system signal integrity. the audiovisual data carried on these high speed channels are encoded by a technique called transmission minimized differ- ential signaling (tmds) and in the case of hdmi, is also encrypted according to the high bandwidth digital copy protection (hdcp) standard. the second group of signals consists of low speed auxiliary control signals used for communication between a source and a sink. depending upon the application, these signals can include the ddc bus (this is an i 2 c bus used to send edid information and hdcp encryption keys between the source and the sink), the consumer electronics control (cec) line, and the hot plug detect (hpd) line. these auxiliary signals are bidirectional, low speed, and transferred over a single-ended transmission line that does not need to have controlled impedance. the primary concern with laying out the auxiliary lines is ensuring that they conform to the i 2 c bus standard and do not have excessive capacitive loading. tmds signals in the hdmi/dvi standard, four differential pairs carry the tmds signals. in dvi, three of these pairs are dedicated to carrying rgb video and sync data. for hdmi, audio data is interleaved with the video data; the dvi standard does not incorporate audio information. the fourth high speed differ- ential pair is used for the av data-word clock, and runs at one-tenth the speed of the tmds data channels. the four high speed channels of the AD8191 are identical. no concession was made to lower the bandwidth of the fourth channel for the pixel clock, so any channel can be used for any tmds signal. the user chooses which signal is routed over which channel. additionally, the tmds channels are symmetrical; therefore, the p and n of a given differential pair are inter- changeable, provided the inversion is consistent across all inputs and outputs of the AD8191. however, the routing between inputs and outputs through the AD8191 is fixed. for example, in quad mode, output channel 0 always switches between input a0, input b0, input c0, input d0, and so forth. the AD8191 buffers the tmds signals and the input traces can be considered electrically independent of the output traces. in most applications, the quality of the signal on the input tmds traces are more sensitive to the pcb layout. regardless of the data being carried on a specific tmds channel, or whether the tmds line is at the input or the output of the AD8191, all four high speed signals should be routed on a pcb in accordance with the same rf layout guidelines. layout for the tmds signals the tmds differential pairs can either be microstrip traces, routed on the outer layer of a board, or stripline traces, routed on an internal layer of the board. if microstrip traces are used, there should be a continuous reference plane on the pcb layer directly below the traces. if stripline traces are used, they must be sandwiched between two continuous reference planes in the pcb stack-up. additionally, the p and n of each differential pair must have a controlled differential impedance of 100 . the characteristic impedance of a differential pair is a function of several variables including the trace width, the distance separating the two traces, the spacing between the traces and the reference plane, and the dielectric constant of the pc board binder material. interlayer vias introduce impedance discontinuities that can cause reflections and jitter on the signal path, therefore, it is preferable to route the tmds lines exclusively on one layer of the board, particularly for the input traces. in some applications, such as using multiple AD8191s to construct large input arrays, the use of interlayer vias becomes unavoidable. in these situations, the input termination feature of the AD8191 improves system signal integrity by absorbing reflections. take care to use vias minimally and to place vias symmetrically for each side of a given differential
AD8191 rev. 0 | page 27 of 32 pair. furthermore, to prevent unwanted signal coupling and interference, route the tmds signals away from other signals and noise sources on the pcb. both traces of a given differential pair must be equal in length to minimize intrapair skew. maintaining the physical symmetry of a differential pair is integral to ensuring its signal integrity; excessive intrapair skew can introduce jitter through duty cycle distortion (dcd). the p and n of a given differential pair should always be routed together to establish the required 100 differ- ential impedance. enough space should be left between the differential pairs of a given group so that the n of one pair does not couple to the p of another pair. for example, one technique is to make the interpair distance 4 to 10 times wider than the intrapair spacing. any group of four tmds channels (input a, input b, input c, input d, or the output) should have closely matched trace lengths to minimize interpair skew. severe interpair skew can cause the data on the four different channels of a group to arrive out of alignment with one another. a good practice is to match the trace lengths for a given group of four channels to within 0.05 inches on fr4 material. the length of the tmds traces should be minimized to reduce overall signal degradation. commonly used pc board material, such as fr4, is lossy at high frequencies; therefore, long traces on the circuit board increase signal attenuation resulting in decreased signal swing and increased jitter through intersymbol interference (isi). controlling the characterist ic impedance of a tmds differential pair the characteristic impedance of a differential pair depends on a number of variables including the trace width, the distance between the two traces, the height of the dielectric material between the trace and the reference plane below it, and the dielectric constant of the pcb binder material. to a lesser extent, the characteristic impedance also depends upon the trace thickness and the presence of solder mask. there are many combinations that can produce the correct characteristic impedance. it is generally required to work with the pc board fabricator to obtain a set of parameters to produce the desired results. one consideration is how to guarantee a differential pair with a differential impedance of 100 over the entire length of the trace. one technique to accomplish this is to change the width of the traces in a differential pair based on how closely one trace is coupled to the other. when the two traces of a differential pair are close and strongly coupled, they should have a width that produces a 100 differential impedance. when the traces split apart, to go into a connector, for example, and are no longer so strongly coupled, the width of the traces should be increased to yield a differential impedance of 100 in the new configuration. tmds terminations the AD8191 provides internal, 50 single-ended terminations for all of its high speed inputs and outputs. it is not necessary to include external termination resistors for the tmds differential pairs on the pcb. the output termination resistors of the AD8191 back-terminate the output tmds transmission lines. these back-terminations act to absorb reflections from impedance discontinuities on the output traces, improving the signal integrity of the output traces and adding flexibility to how the output traces can be routed. for example, interlayer vias can be used to route the AD8191 tmds outputs on multiple layers of the pcb without severely degrading the quality of the output signal. auxiliary control signals there are four single-ended control signals associated with each source or sink in an hdmi/dvi application. these are hot plug detect (hpd), consumer electronics control (cec), and two display data channel (ddc) lines. the two signals on the ddc bus are sda and scl (serial data and serial clock, respectively). these four signals can be switched through the auxiliary bus of the AD8191 and do not need to be routed with the same strict considerations as the high speed tmds signals. in general, it is sufficient to route each auxiliary signal as a single-ended trace. these signals are not sensitive to impedance discontinuities, do not require a reference plane, and can be routed on multiple layers of the pcb. however, it is best to follow strict layout practices whenever possible to prevent the pcb design from affecting the overall application. the specific routing of the hpd, cec, and ddc lines depends upon the application in which the AD8191 is being used. for example, the maximum speed of signals present on the auxiliary lines is 100 khz i 2 c data on the ddc lines; therefore, any layout that enables 100 khz i 2 c to be passed over the ddc bus should suffice. the hdmi 1.2a specification, however, places a strict 50 pf limit on the amount of capacitance that can be measured on either sda or scl at the hdmi input connector. this 50 pf limit includes the hdmi connector, the pcb, and whatever capacitance is seen at the input of the AD8191, or an equivalent receiver. there is a similar limit of 100 pf of input capacitance for the cec line. the parasitic capacitance of traces on a pcb increases with trace length. to help ensure that a design satisfies the hdmi specification, the length of the cec and ddc lines on the pcb should be made as short as possible. additionally, if there is a reference plane in the layer adjacent to the auxiliary traces in the pcb stack-up, relieving or clearing out this reference plane immediately under the auxiliary traces significantly decreases the amount of parasitic trace capacitance. an example of the board stackup is shown in figure 32 .
AD8191 rev. 0 | page 28 of 32 pcb dielectric layer 1: signal (microstrip) silkscreen silkscreen pcb dielectric pcb dielectric layer 2: gnd (reference plane) layer 3: pwr (reference plane) layer 4: signal (microstrip) w 3w 3w reference layer relieved underneath microstrip 06123-010 figure 32. example board stackup hpd is a dc signal presented by a sink to a source to indicate that the source edid is available for reading. the placement of this signal is not critical, but it should be routed as directly as possible. when the AD8191 is powered up, one set of the auxiliary in- puts is passively routed to the outputs. in this state, the AD8191 looks like a 100 resistor between the selected auxiliary inputs and the corresponding outputs as illustrated in figure 27 . the AD8191 does not buffer the auxiliary signals, therefore, the input traces, output traces, and the connection through the AD8191 all must be considered wh en designing a pcb to meet hdmi/dvi specifications. the unselected auxiliary inputs of the AD8191 are placed into a high impedance mode when the device is powered up. to ensure that all of the auxiliary inputs of the AD8191 are in a high impedance mode when the device is powered off, it is necessary to power the amuxvcc supply as illustrated in figure 28 . in contrast to the auxiliary signals, the AD8191 buffers the tmds signals, allowing a pcb designer to layout the tmds inputs independently of the outputs. power supplies the AD8191 has five separate power supplies referenced to two separate grounds. the supply/ground pairs are: ? avcc/avee ? vtti/avee ? vtto/avee ? dvcc/dvee ? amuxvcc/dvee the avcc/avee (3.3 v) and dvcc/dvee (3.3 v) supplies power the core of the AD8191. the vtti/avee supply (3.3 v) powers the input termination (see figure 25 ). similarly, the vtto/avee supply (3.3 v) powers the output termination (see figure 26 ). the amuxvcc/dvee supply (3.3 v to 5 v) powers the auxiliary multiplexer core and determines the maximum allowed voltage on the auxiliary lines. for example, if the ddc bus is using 5 v i 2 c, then amuxvcc should be connected to +5 v relative to dvee. in a typical application, all pins labeled avee or dvee should be connected directly to ground. all pins labeled avcc, dvcc, vtti, or vtto should be connected to 3.3 v, and pin amuxvcc tied to 5 v. the supplies can also be powered individually, but care must be taken to ensure that each stage of the AD8191 is powered correctly. power supply bypassing the AD8191 requires minimal supply bypassing. when powering the supplies individually, place a 0.01 f capacitor between each 3.3 v supply pin (avcc, dvcc, vtti, and vtto) and ground to filter out supply noise. generally, bypass capacitors should be placed near the power pins and should connect directly to the relevant supplies (without long inter- vening traces). for example, to improve the parasitic inductance of the power supply decoupling capacitors, minimize the trace length between capacitor landing pads and the vias as shown in figure 33 . extra added inductance recommended not recommended 06123-033 figure 33. recommended pad outline for bypass capacitors
AD8191 rev. 0 | page 29 of 32 in applications where the AD8191 is powered by a single 3.3 v supply, it is recommended to use two reference supply planes and bypass the 3.3 v reference plane to the ground reference plane with one 220 pf, one 1000 pf, two 0.01 f, and one 4.7 f capacitors. the capacitors should via down directly to the supply planes and be placed within a few centimeters of the AD8191. the amuxvcc supply does not require additional bypassing. this bypassing scheme is illustrated in figure 34 . AD8191 a uxiliary lines tmds traces decoupling capacitors 06123-034 figure 34. example placement of power supply decoupling capacitors around the AD8191
AD8191 rev. j | page 30 of 32 outline dimensions compliant to jedec standards ms-026-bed top view (pins down) 1 25 26 51 50 75 76 100 0.50 bsc lead pitch 0.27 0.22 0.17 1.60 max 0.75 0.60 0.45 view a pin 1 1.45 1.40 1.35 0.15 0.05 0.20 0.09 0.08 coplanarity view a rotated 90 ccw seating plane 7 3.5 0 14.20 14.00 sq 13.80 16.20 16.00 sq 15.80 051706-a figure 35. 100-lead low profile quad flat package [lqfp] (st-100) dimensions shown in millimeters ordering guide model temperature range package description package option ordering quantity AD8191astz 1 ?40c to +85c 100-lead low profile quad flat package [lqfp] st-100 AD8191astz-rl 1 ?40c to +85c 100-lead low profile quad flat package [lqfp], reel st-100 1,000 AD8191-eval evaluation kit 1 z = pb-free part.
AD8191 rev. 0 | page 31 of 32 notes
AD8191 rev. 0 | page 32 of 32 notes purchase of licensed i 2 c components of analog devices or one of its sublicensed associ ated companies conveys a license for the purchaser under the phil ips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips . ?2006 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d06123-0-10/06(0)

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